1. Field of the Invention
The present invention relates to a data storage apparatus and a data measuring apparatus. More particularly, the invention relates to a data storage apparatus and a data measuring apparatus suitable for analyzing a semiconductor device that incorporates a plurality of function blocks for implementing specific functions.
2. Description of the Background Art
FIG. 8 is a block diagram of a conventional data measuring apparatus 10 and a memory-embedded device 12 connected to the apparatus 10. The memory-embedded device 12 is a semiconductor device incorporating a plurality of function blocks. In FIG. 8, the device 12 comprises an SRAM block 14 functioning as a static random access memory (SRAM), a DRAM block 16 acting as a dynamic random access memory (DRAM), a flash block 18 working as a flash memory, an analog block 20 composed of a relevant analog circuit, and a logic block 22 made of a suitable logic circuit.
The data measuring apparatus 10 is constituted by a tester 24, a scrambling circuit 26, and a storage device 28. Inside the tester 24 are a pattern generator 30 that generates test patterns necessary for analyzing the memory-embedded device 12, and a judging circuit 32 that judges whether the device 12 is functioning normally.
More specifically, the pattern generator 30 supplies the memory-embedded device 12 with address signals and a variety of input data for determining locations of parts under test. Furthermore, the pattern generator 30 feeds the scrambling circuit 26 with the same addresses sent to the memory-embedded device 12, and supplies expected values to the judging circuit 32 for data judgment purposes.
Relevant data are written as requested by the pattern generator 30 to memory cells constituting the SRAM block 14, DRAM block 16, or flash block 18 in the memory-embedded device 12. The data thus written to the memory cells are retrieved as requested by the pattern generator 30 and sent to the judging circuit 32. In turn, the judging circuit 32 compares the output signal from the memory-embedded device 12 with an expected value for data judgment to see if the device 12 is functioning normally. The result of the judgment is fed to the scrambling circuit 26.
The scrambling circuit 26 converts addresses sent from the pattern generator 30 according to suitable rules, and processes error data or the like from the judging circuit 32 in accordance with relevant rules. After such conversion and processing, the scrambling circuit 26 sends the converted address signals and the processed error data to the storage device 28. As a result, the processed error data or the like are stored at those locations in the storage device 28 which are identified by the converted address signals.
Generally, the plurality of memory blocks incorporated in the memory-embedded device 12 are each addressed by a specific addressing method. These memory blocks usually have a different memory size each. This means that if the address signals from the pattern generator 30 are sent unmodified to the storage device 28 so as to identify data storage locations therein, it will be impossible to store efficiently the data about the multiple memory blocks of the different types.
The scrambling circuit 26 is designed to store efficiently into the storage device 28 the data about the multiple memory blocks. Depending on the type of memory block under test, the scrambling circuit 26 produces a plurality of states in which to convert address signals and to process error data or the like according to relevant rules. More specifically, the scrambling circuit 26 establishes one of three settings A, B and C in accordance with an externally supplied switching signal. Bringing the setting A, B or C into effect allows the data about the SRAM block 14, DRAM block 16 or flash block 18 to be stored efficiently. The data measuring apparatus 10 alters the settings of the scrambling circuit 26 in such a manner that the status of the memory-embedded device 12 housing a plurality of memory device may be measured continuously and that the measurements may be stored efficiently into the storage device 28.
The conventional scheme above has a number of disadvantages. It takes at least several microseconds for the scrambling circuit 26 to have its settings switched. In fact, actually altering the circuit settings requires a longer stop time due to a processing of setting information other than the several microseconds. Semiconductors are usually tested at intervals of tens of nanoseconds. This makes it impossible for the conventional scrambling circuit 26 to have its settings modified in real time while a semiconductor device is being tested.
The conventional scrambling circuit 26 has its workable settings determined in advance. It follows that this type of scrambling circuit 26 is not suitable for general-purpose use with diverse kinds of semiconductor devices. Although the versatility of the scrambling circuit 26 could be enhanced by preparing a large number of settings that may be established, the preparation would require increasing the number of pins needed for the switchover involved. This imposes certain constraints on the practice of furnishing numerous pins beforehand to provide many viable settings.